1. Field of the Invention
The present invention relates to a semiconductor device that enables parallel operation of external output and external input, and particularly relates to a technique for reducing a noise caused by an undesired inductance component parasitizing a package substrate mounted with a semiconductor integrated circuit. For example, the invention relates to a technique effective for use in a quad static random access memory (quad SRAM) in which external data output operation timing can be varied with respect to input operation of external multi-bit data.
2. Description of Related Art
When current change occurs in a signal transfer system, noise voltage in proportion to self-inductance is produced, in addition, when current change occurs in an adjacent, and different signal transfer system, noise voltage is also produced in proportion to mutual inductance. When a wiring of an external data output system and a wiring of an external data input system are adjacent vertically or horizontally in a package substrate of a semiconductor substrate, if an external output condition is changed during external data input operation, current change in the output system induces noise voltage in the input system in accordance with the mutual inductance. Therefore, if input operation timing is specified such that the input timing is always in a period of determining output operation, input data are not significantly distorted by the output operation. Patent document 1 describes a technique of reducing a crosstalk noise due to mutual inductance in a semiconductor integrated circuit.
In a package structure using a full grid, ball grid array (BGA) having package terminals, a semiconductor integrated circuit having a WPP (wafer process package) structure having solder bump electrodes as outer terminals is mounted on a package substrate having BGA, the solder bump electrodes being to be connected to pad electrodes via leader wirings. Since connection between respective wiring layers needs be performed via through-holes in a multilayer wiring package substrate, the through-holes needs to be formed avoiding positions of BGA balls and solder bumps. Therefore, it is desirable that the BGA balls and the solder bumps are disposed such that they are overlapped in viewing in a stacking direction of the semiconductor integrated circuit and the package substrate in order to arrange the through-holes of the package substrate orderly or regularly. Patent document 2 describes a technique of disposing the balls and the bumps with being overlapped in such a way.
Patent document 1: JP-A-11-135668.
Patent document 2: JP-A-2001-203298.
The inventor has investigated reduction in mutual inductance between an external output signal system and an external input signal system, in which parallel operation is enabled, in a semiconductor device having a BGA package structure. When the through-holes formed in the package substrate is disposed orderly and regularly as described in the Patent document 2, the number of places where the through-holes are partially concentrated can be decreased, consequently the degree of freedom of wiring paths formed on the package substrate is increased, and the degree of freedom of spacing or shielding between the external output signal system and the external input signal system, in which parallel input/output operation is enabled, can be increased.
However, it is not enough to sufficiently reduce mutual inductance. The inventor had the following knowledge from investigation. First, when the semiconductor integrated circuit having the WPP structure is mounted on the BGA package substrate, a wiring layer as a top layer of the BGA package substrate is directly opposed to leader wirings connecting between the solder bumps and the pad electrodes, and a shield layer is not provided between them. When a wiring of an external output signal system and wiring of an external input signal system exist as wirings opposed in such a way, a noise are added to an external input signal. The inventor found that allocation of a major wiring to the top wiring layer of the package substrate is particularly important in this sense. That is, importance of function allocation to wiring layers of the semiconductor package substrate is increased. On the other hand, it was found that since leader wirings from the pad electrodes to the solder bumps in the WPP structure of the semiconductor integrated circuit was necessary to be in a planar layout, an inductance component was necessary to be effectively reduced in the planar layout in the leader wirings.